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RE: Logic Design - How to write simple RAM in VHDL
Ah... VHDL, Xilinx, FPGA, State Machine, and red raport 😂
I hope I can see this kind of tutorial to reminiscing the old day.
Ah... VHDL, Xilinx, FPGA, State Machine, and red raport 😂
I hope I can see this kind of tutorial to reminiscing the old day.
Oh no you got me!
I'm thinking of implementing something "big" that will of course contain a State machine (FSM) and will then be uploaded to a Xilinx FPGA (I will buy a relatively good one in the Summer).
So, be prepared! More is yet to come!
This is just the beginning :D