Logic Design - VHDL Basic Circuits

in #logic5 years ago (edited)

 

    Hello again! Its a me drifter1! Today, we continue our Series of Logic Design writing some "Basic" Circuits in VHDL, using the stuff that we learned last time! We will write a Basic AND Gate, for you to understand direct assignments. Then we will use the Assignment Statements when-else and with-select to write a simple multiplexer. Lastly, I will write the same multiplexer using a process case statement! So, without further do, let's get started!


Direct Assignments:

    When assigning a specific boolean function to an output that VHDL Code is pretty simple. To make this you have to know the Output function and then we just have to write a Expression that contains the Inputs and gives us the Output. If you remember from last time, we use a "<=" when assigning. So, when directly assigning a Output/Signal we simply have to write a statement that contains this arrow inside of our Architecture!

    To understand it more, let's write a AND Gate using VHDL Code. A AND Gate has 2 Inputs and 1 Output that we will write inside of the Entity. Then inside of the Architecture for this Entity we simply have to assign the output to the "and" operation between those Inputs. And this is actually it!

So, our Code looks like this:

library ieee;
use ieee.std_logic_1164.all;
-- define entity
entity and2_gate is
port(
    -- inputs
    a, b: in std_logic;
    -- outputs
    c: out std_logic
);
end and2_gate;
-- define architecture
architecture arch of and2_gate is
    begin
    -- assign output to and operation between inputs
    c <= a and b;
end arch;


    You can see that it is actually pretty easy to write down such a simple Gate! This way of writing a Circuit is called Dataflow and we will talk about those more specificly some posts later on. I hope that you can see that it's pretty easy to assign the Outputs just to Expressions that contain the Inputs, but as you might remember, this function may be really complex and we also don't know how the Circuit is gonna look like, cause the compiler does what it wants!


Assignment Statements:

    Writing down a Circuit using when-else or with-select Statements is also not so difficult. We prefer this way only when we know the Behaviour or Truth Table of our Circuit! This and also the representation using Processes is called Behavioral (we will talk about more some posts later again). So, we prefer this way of writing when the Truth Table is pretty small or simple, when the Functions are too complex to simpify or when-else :D

Let's write down a simple 4-t0-1 Multiplexer using a when-else statement to assign the Output:

library ieee;
use ieee.std_logic_1164.all;
-- define entity
entity mux4x1 is
port(
    -- "i" inputs
    i1, i2, i3, i4: in std_logic;
    -- selection lines
    s: in std_logic_vector(1 downto 0);
    -- output
    y: out std_logic
);
end mux4x1;
-- define architecture
architecture arch of mux4x1 is
    begin
    y <= i1 when s = "00" else
         i2 when s = "01" else
         i3 when s = "10" else
         i4 when s = "11";
end arch;


Let's redo this but using a with-select statement:

library ieee;
use ieee.std_logic_1164.all;
-- define entity
entity mux4x1 is
port(
    -- "i" inputs
    i1, i2, i3, i4: in std_logic;
    -- selection lines
    s: in std_logic_vector(1 downto 0);
    -- output
    y: out std_logic
);
end mux4x1;
-- define architecture
architecture arch of mux4x1 is
    begin
   with s select y <=
        i1 when "00",
        i2 when "01",
        i3 when "10",
        i4 when "11";
end arch;


I hope that you know understood how we use this type of stuff!


Processes:

    Let's now lastly talk about Processes. We use Processes mostly in Sequential Circuits, because of the "activation" on signal property! But, Sequential Circuits are not today's topic and will be discussed by their own. So, when do we use Processes else? Well, its pretty simple. We again use them for Behavioral Coding, instead of a when-else or with-select Statement. 

So, let's write down the same MUX as before but using a case statement inside of a process:

library ieee;
use ieee.std_logic_1164.all;
-- define entity
entity mux4x1 is
port(
    -- "i" inputs
    i1, i2, i3, i4: in std_logic;
    -- selection lines
    s: in std_logic_vector(1 downto 0);
    -- output
    y: out std_logic
);
end mux4x1;
-- define architecture
architecture arch of mux4x1 is
    begin
    -- define process
    process(s(1), s(0))
    begin
    -- case statement
    case s(1 downto 0) is
          when "00" =>  y <= i1;  
          when "01" =>  y <= i2;
          when "10" =>  y <= i3;
          when "11" =>  y <= i4;
    end case;
    end process;
end arch;


I hope that you understood some stuff even more now after all this simple Example Codes!

And this is actually it! Hope you enjoyed it!

    Next time in VHDL we will get into a small Introduction to the Software called ModelSim that we will use for Simulation Purposes! I will give you some information about how we use it and run also the Codes from today and some other new Examples to test out the Output and get you familiar with the Environment.

Bye!

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