Logic Design - Latches and Flip Flops
(I searched Google and found Flip Flops, but not the ones I was looking for xD but it's funny I guess)
With this funny but yet describing picture we start out today's second post! Yeah, I am crazy, all my posts take so much research time, but I manage to upload 2 in one day sometimes... Let's talk about the post now! We will get into Latches and Flip Flops that are the building blocks of the Sequential Circuits that we will talk about tomorrow! We will talk about the different kinds of Latches and Flip Flops and why the last are more commonly used! So, let's get straight into it now!
Let's first start out with why we need Latches and Flip Flops and what the difference is. Both store their state information in form of 1-bit. There are 2 Stable States (0 or 1) in which we can put a Latch or Flip Flop, controlling them from their Input.
The difference is simple. Flips Flops are actually Latches that work synchronous (and not asynchronous like Latches). That means that a Flip Flop changes output only when the input changes during a specific clock event, but an Latch changes directly. So, an Flip Flop is Edge-Sensitive and an Latch is Level-Sensitive!
The clock event that an Flip Flop waits for can be one of 2: Negative (1->0 falling edge) or Positive (0->1 rising edge) Edge Switch. The first ones are called negative edge-triggerred and the second ones positive edge-triggered! We mostly use the positive ones that change Output when the Clock's Output changes from 0 to 1.
So, let's now get into Latches!
There are several types of Latches and many of those have a flip-flop partner. We will talk about SR (Set-Reset), JK and D (Data) Latches.
There are many types of SR Latches. All of them have 2 Inputs S, R and 2 Outputs Q, Q', where the Inputs S and R stand for Set and Reset and the Outputs are the normal output Q and the Inverted Q (Q').
The most fundamental and simple one is the SR NOR Latch, that can be created using 2 NOR Gates.
Having both Inputs 0 the Latch keeps it's state! When Reset is 1, the Output Q resets itself to 0 (Q' gets 1). When Set is 1, the Output Q is set to 1 (Q' gets 0). We can't have both be 1, cause that's a restricted state.
Using the same logic we can create an (SR)' NAND Latch using 2 NAND Gates and having the Inputs inverted!
The Truth Table is the same as an SR NOR Latch, but the inputs are inverted!
A JK Latch works similar to an SR Latch, but this time the forbidden 1,1 Input toggles the Output! Everything else stays the same.
We don't use JK Latches but JK Flip Flops, cause the Toggling doesn't make so much sense in Latches. It would continuously jump from 0 to 1 and vise versa.
The Gated D Latch has 2 Inputs called D and E, where the second one is an Enable signal that needs to be active (1) for changes, cause else the Latch will keep it state. It actually uses an SR NOR Latch as basis and does some tweaking to make the first input of the SR Latch be D's complement using an AND Gate.
That way the Output becomes 0 when E is 1 and D is 0 and the Outputs becomes 1 when E and D are both 1! In every other state the State gets stored, cause we can have a change only when E get's activated.
Let's now get into Flip Flops! I will talk about D (Data), JK and T (Toggle) Flip Flops. All Flip Flops have one thing in common, they change Output only when a specific edge clock event occurs. So, the Output will change when the Inputs have the specific needed value and the clock is on an rising or falling edge depending on the type! To keep things simple I will talk about rising-edge or positive edge-triggered Flip Flops.
D Flip Flop:
A D Flip Flop works exactly like an D Latch, but this time the Enable Input will be changed by an Clock Input! So, the state (Output) will be kept, if we are not in an rising edge.
JK Flip Flop:
A JK Flip Flop works like an JK Latch, but this time (as I already said) toggling makes sense and so this Flip Flop becomes pretty useful! The only difference is that this circuit contains another Input that it gets from an CLK. So, the Truth Table of the JK Latch will work only when the Clock is on an rising edge, else the JK Flip Flop will keep it's state!
T Flip Flop:
A T Flip Flop is used for toggling like an JK Flip Flop, but there are some differences. An T Flip Flop switches only when T is 1 and keeps it's state when T is 0. So, a T Flip Flop doesn't have a way of defining a specific Output, but it can only Toggle the Output directly from 0 to 1 and vise versa.
This is actually it! Hope you enjoyed this post!
Next time in Logic Design we will get into Sequential Circuits!
Until next time...Bye!