There is a specific hardware unit that stores the N value in a changeable way. However, to achieve this change a “firmware upgrade” is needed. This means that some sort of dynamism has to be put in the ASIC board and anything that is able to “adapt” directly leads to a huge decrease in performance. The board that comes out is an hybrid between an FPGA and an ASIC.

Haha yeah im wrong on the memory part but the devs have proven to adapt to asics being developed which is as resistant as it gets imo. You're right that an algo in itself isn't very resistant but what incentive is there to make an fpga asic for vertcoin when the asics made require firmware upgrades and the devs have proven to respond to asics developed relatively quick?

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