BOOLR Digital Logic Simulation | JK Flip-Flop logic simulation

What is JK Flip-Flop?

A JK Flip-Flop is a refinement of an RS Flip-Flop with an indeterminate state of RS type defined as J and K. Inputs J and K are like input S and R to set and clear the flip-flop, respectively. When both input J and K is high (1), the flip-flop switches to its complement state, which is, if Q = 1, it switches to Q = 0.

Intended Learning Outcome (What Will I Learn?)

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After reading and participating in this tutorial, the readers should be able to:

• learn how to implement an JK FLIP-FLOP logic circuit;
• create a digital logic circuit for JK FLIP-FLOP simulation ; and,
• simulate the created JK FLIP-FLOP simulation digital logic circuit.

Requirements

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To be able to follow this tutorial, you should have the following tools at hand:

• A desktop PC or laptop with Windows (7, 8, 10) operating system; and,
• A BOOLR latest release version which you can download at its Github repository GGBRW/BOOLR or vist its website at boolr.me

Difficulty

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• Intermediate

Part 1: Setting up a new project the BOOLR app.

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1 | Open BOOLR.exe from the downloaded latest release zip file of the app.

2 | Create a new project by clicking NEW BOARD.

Then, you will be directed to Create New Board where you are ask to type in the name of the new board.

Type in the board name. For this tutorial, lets have "JK Flip-Flop " as board name.

3 | Click to finalize setting up a new project.

For the basic operations and functions of the BOOLR Digital Logic Simulation, you are advise to read the Introduction to BOOLR.

Part 2: Creating a JK Flip-Flop Digital Logic Circuit in BOOLR

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1 | We start by creating a basic flip-flop composed of two NOR gates where one input is connected with the other input. Start by selecting and OR gate; and placed it in a manner that is spaced properly. Next, add a NOT gate to complete the NOR gate configuration.

Connect the output of NOR(a) to one of the input of NOR(b). Do it also for the ouput of NAND(b). In this way we can set the sequential operation a flip-flop, where input are dependent on each NAND gates response.

2 | Add a two set of AND gate that will set the J and K input processor.

4 | Select input devices from . From the menu click on INPUT.

6 | Add an input before the AND gate. The upper AND gate is set for J and the other for K.

7 | Add an input clock pulse in between inputs J and K. Enable this component by clicking on . From the drop-down option, select Clock.

8 | Once you've added the clock, a time delay editor appears. Set the time delay to your preference. For this tutorial, I will set the time delay to 1000 ms. The clock will set the time response of enabling the two other inputs.

9 | Connect the clock on one of the inputs in both AND gates. The clock pulse set or enables the J and K input.

10 | And another set of AND gates that will serve as an additional input terminal before the Flip-Flop. Connect the output of the preceding AND gate to the new AND gate. For the other terminal, connect the output of the NOR gates. This will make J and K inputs indeterminate.

11 | Connect the output from the new set of AND gate to the input R and S of a regular Flip-Flop.

12 | Add two LED after the NOT gate at the right most AND gates. To add the component, you need first to enable and click at the location where you want it to add.

Part 3: Simulation of the created JK Flip-FLop

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How does JK FLIP-FLOP works?

A JK Flip-Flop is constructed with two-crosslink NOR gates and two three terminal AND gate. (In our simulation, we set two cascaded AND gates to perform the operation of a three terminal AND gate.) The output Q (from NOR(a) is ANDed with K and CP (clock pulse) inputs so that the flip-flops is cleared during a clock pulse only when it is previously high (1) state. Similarly, the Q' (NOR(b) output ) is also ANDed with J and CP inputs so that the flip-flops is cleared during a clock pulse only when it is previously high (1) state. When both J and K are high (1), the input pulse is transmitted through one AND gate only where the present value of either Q or Q' is high (1).

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1 |Verify the simulation button if it is play or paused. Pause button indicates simulation is going on, while Play button signifies the simulation is paused.By default, the BOOLR app is always on simulation.

You would notice in the output LED a changes state as the input clock change state after 1000 ms.

2 | Verifying our discussion earlier, input the values for J and K to 1. Observe the result at the OUTPUT. To change the values of input, click on the number inside the input symbol.

To clearly understand the result, watch the actual recording of the simulation. This will also your basis if you have followed the tutorial completely. Your simulation should the same with the recordings.

Result of Simulation:

Watch the video clip below for the actual recording of JK Flip-Flop simulation.

Curriculum

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You can browse the other curriculum for BOOBLR Digital Logic Simulator.

• Introduction to BOOLR Digital Logic Simulation
• Half Adder
• Full Adder
• Half Subtractor
• Full Subtractor
• Exclusive-OR implemented with AND-NOT-OR gates
• Exclusive-NOR implemented with AND-NOT gates
• Flip-Flop
• RS Flip-Flop
• D Flip-Flop

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Posted on Utopian.io - Rewarding Open Source Contributors

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