Every beginner radio amateur drew attention to the extra loop of unknown purpose on the printed circuit boards. Why stick to the track, to create additional interference if more rational to make a straight path?

Why stick to the track?

electrical signal speed is the speed of light. Hurry this is nothing. A second electrical signal travels 299,792,458 meters! It's almost like the Earth to the Moon. It would seem - and here our little track? Let's take a look at the levels of a data bus.

The levels of the SPI bus signals

The diagram of the clock signal during one cycle is indicated by the letter T. Let's calculate its length if the bus speed (as well as the frequency of the clock signal in this case) = 1MHz.

299 792 458 m / 1 million times = 299.79 meters.

While nothing to worry about. Now imagine that the bus frequency = 2 GHz. Then the length of the period of one cycle is obtained = 15 cm Imagine for clarity an example -. We built a fee and the length of the track clock turned = 4 cm and a length of track data = 20 cm This means that when the end of the clock track over the first measure. signal on a track with the data will be even more on the way.

The clock path to run a cycle and started for the second bit. On the data path while edinichka not yet reached. If the data are identified at the upstream edge (ie. E. When the clock signal transition from 0 to 1), the second bit = 0 is obtained too, as the first bit of 1 has not yet reached the end of the track and its yedinichku 0. We will see only third bit! If the data are identified with falling edge of the clock signal, then we will see in the second yedinichku bit from the first bit.

Hence the conclusion:

for identification data when the clock signal rising edge, the length of the data track to be the same length or shorter than the maximum of a half period of the clock signal.

to identify data in a down edge of the clock signal, the length of the data path should be the same length or longer than a maximum of a half period of the clock signal.

Admission to the half period is taken arbitrarily, as it still is necessary to consider the speed of the receiving chip. E. There is less tolerance.

Tolerance (or upper or lower) = 299 792 458 / (2 * Chastota_taktovogo_signala) - 299 792 458 / skorost_pereklyucheniya_porta_priёmnika.

If the track is situated between two solid conductive layers, the resulting tolerance must be reduced by half (for PCB).

Sometimes specifications explicitly specify a tolerance of the difference in length of the tracks.